Verilog: Reading 1 bit input and Writing it to 288 bit reg -


In verilog, I have a module name (input data, ..., output ...);
Data is only a bit input and I want to compare the code reg [288: 0] data_tmp; needs to be displayed on how can I transfer data (input) reg?

I tried to handle it in C as an array so that it could be used for a loop:

Actual

But it does not recognize any of the values ​​or overwrites it.

Actual code: 

  module inspector (input RSTN, data, CLK, output total count, SkypeCanc, FTPCNT, NSTCNT, telnet_content, SSHCNT, SNMPCNT, SMTPPNt, NNTPCNT, Telnet_session , Skype_session, sh_season); Output [31: 0] total_cnt; Output [7: 0] skype_cnt; Output [7: 0] ftp_cnt; Output [7: 0] https_cnt; Output [7: 0] Telnet_con; Output [7: 0] ssh_cnt; Output [7: 0] snmp_cnt; Output [7: 0] smtp_cnt; Output [7: 0] nntp_cnt; Output [7: 0] Telnet_sation; Output [7: 0] Skype_session; Output [7: 0] ssh_session; Local Param IIT = 0; Local data = 1; Local ports = 2; Local primary number = 3; Reg [287: 0] data_tmp; Reg [3: 0] start_profession = 32'h 5 a5a5a5; Reg [1: 0] state; Integer I; Always @ (posedge clk) if (rst_n) total_cnt_tmp = 8'h00; .... ssh_session_tmp = 8'h00; Start and end case (state) for INIT: (i = 0; i <288; i = i + 1) data_tmp [i] = data start; End if (data_tmp [31: 0] == start_failed success) state starts < = DATA; End and State of the State & lt; = INIT; End of End .....    
 
 
 Replacing for-loop data ; That is, if  data  is 1, then you get 288 people, if you have  data  0 then you get 288 zeros. Do you want to move the  data_tmp  byte or bits on the right, based on the order of the bit code what a worker is.  
  data_tmp & lt; = {data_tmp [286: 0], data}; // shift and left   
 or  
  data_tmp & lt; = {Data, data_tmp [287: 1]}; // Change and fill right   
 Also, remember to hand over the flop with non-blocked ( & lt; = ). Blocked ( = ) to specify composition logic.

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