makefile: variable evaluation in function call? -


I have a makefile like this: 

  DIRS = foo bar   
 I want to enumerate the files in the sub-directories of these directories, so I can pass them all to the program at once. It is not working:  
  UNIT_FILES = () find_units: c for $ (DIRS); Do UNIT_FILES + = ($ (wildcard $ (c) / systemd / *));   
 However, it works:  
  UNIT_FILES = () find_units: UNIT_FILES + = ($ (wildcard foo / systemd / *))   
 So I know this issue is  wildcard  in the call with my variable evaluation. I've tried to differentiate it, which is like  $ (c) ,  $$ c  and I like it, but I'm just stabs here in the dark.  
 Can anyone tell me in the right direction?   
 
 
 here:  
  $ c (dirs); Do UNIT_FILES + = ($ (wildcard $ (c) / systemd / *));   
 You are using a shell, which will be called in such a way:  
  $ (SHELL) -c "$ c for $ (DIRS); UNIT_FILES + = ($ (Wildcard $ (C) / SystemDi / *)) ""   
 Nothing is actually expanded in UNIT_FILES because this command is not executed Makefile Level.  
  UNIT_FILES + = $ (foreach DIR, $ (DIRS), $ (wildcard $ (dir) / systemd / /))   
 How it can be expanded:  
  UNIT_FILES + = $ (wildcard Foo / SystemD / *) $ (Wildcard Bar / SystemDi / *)

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