arm - Linaro g++ aarch64 compilation cause unalignment fault -


I am using Limarro G ++ for ARM arch64 to compile a simple CPP file: 

  int main () {char * helloMain = "main module (crm.c)"; Long faculty, number = 12; Int stop, main loop = 1; Four words [80] = ""; }   
 generated alpha file after the generated code, I found its asm code:  
  0000000000001270 : int main () {1270: d101c3ff sub sp, sp, # 0x70 char * Helloman = "main module (crm.c)"; 1274: 90000020 ADRP x0, 5000 & lt; _malloc_trim_r + 0x160 & gt; 1278: 9111 c XX, X, # 0x470, 127C: F90003FLLX, [SP] long faculty, number = 12; 1280: d 2800180 movz x0, # 0xc 1284: f90007e0 str x0, [sp, # 8] int stop, main loop = 1; 1288: 52800020 movz w0, # 0x1 128c: B9003Err w0, [SP, # 16] four words [80] = ""; 1290: 910063e0 X 0, SP, # 0x18 12 9 4: 90000021 ADRP x1, 5000 & lt; _malloc_trim_r + 0x160 & gt; 1298: 91122021X1, X1, # 0x488129C: 39400021 LDR Y1, [x1] 12 A: 3 9 000001 SRB Y1, [x0] 12 A4: 91000400 Add X, X0, 0 0x112A8: A9007C1FSTP XZR, XZR, [x0] 12 CA: A9017c1f stp xzr, xzr, [x0, # 16] 12b0: a9027c1f stp xzr, xzr, [x0, # 32] 12b 4: A 9037C1f stp xzr, xzr, [x0, # 48] 12b8: f900201f str xzr, [x0, # 64] 12BC: B900481FRR wzr, [x0, # 72] 12c0: 7900981 F. Strz wzr, [x0, # 76] 12c4: 3901381F Strub wzr, [x0, # 78]} 12c8: 52800000 movz w0, # 0x0 12cc: 9101c3ff Before executing this code on ARMV 8 board, SAP, SP , # 0x70 12d0: d65f03c0 ret   < P> Add  sp  is created at 0x1000 address formed on it.  
 The execution of such code raised an alignment exception exception at 12 A8: a9007c1f stp xzr, xzr, [x0]  
 I saw  x0  Code> 0x1  was therefore aligned to  0x1 , when the  stp  instruction was executed.  
 Why G ++ did this to avoid the alignment fault exception of  0x10 ?  
 The G ++ version is:  
  GCC 4.8.1 20130506 (Preheganz) (Crosstool- 1.13.1-4.8-2013.05 - Linaro GCC 2013.05)  
 
  code> 
  -mno-unaligned-access   
 Enables read and write (or disabled) 16- and 32-bit values ​​from those addresses that are 16- or 32-bit are not aligned. Default unchecked access to all pre-ARMV6 and all ARMv6-M architectures is disabled, and  for all other architectures  is enabled if uncontrolled access is not enabled then the words in pack data structures are A byte will be delivered in time.  
 ARM attribute tag_ CPU_unaligned_access The object generated will be set on either the right or the wrong in the format of this option. If unchecked access is enabled then the preprocessor symbol __ARM_FEATURE_UNALIGNED will also be defined.   
 AArch64 / ARMv8 supports uncontrolled access outside the box, so the GCC assumes that it is available. If this is not the case, then you may have to disable it with a clear up switch. It is also possible that you have not yet completed the "prelace" version and there are various bugs / issues present. By the way, the code behaves like this because GCC literally means the assignment:   
  •  Copy the string "" (so just a zero byte) to start the buffer Create  
  •  Fill the remaining buffer with zero.   
     I suspect that if you enable optimization, then unreachable reach will occur. Or, if you use the  four words [80] = {0} , then it should go to zero once.   

     

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